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Design of FIR Filter on FPGAs using IP cores

Apurva Singh Chauhan, Vipul Soni

The paper describes the development of FIR filters on Field programmable gate array (FPGAs) using IP cores. FIR filter has been designed and realized by FPGA for filtering the digital signal. The implementation of FIR filter on a Xilinx XC3S400FPGA is considered and the coefficients are computed through the Hamming windowing technique. The model is capable of performing filtering operations like low pass, high pass, band pass and band stop based on selection that is embedded into the design. The most basic functions required for nearly any signal processor include addition, multiplication and delays. The filter is set to 16-bit signed data processing. IP Corse has been used to filter the input data. The design is coded through VHDL (hardware descriptive language). To verify the designed outputs simulation, compilation and synthesis have been done. To test the correctness of the design the observed output is compared with the calculated output results from MATLAB implementation that confirms the effectiveness of the design.